1. Field of the Invention
The present invention relates generally to dense SRAM (Static Random Access Memory) cells fabricated with selective SOI (Silicon On Insulator) which involves the selective placement of buried oxide only in the areas where it is needed, and more particularly pertains to soft error hardened, high speed, low power, dense SRAM cells fabricated with selective SOI and their method of fabrication.
2. Discussion of the Prior Art
SRAM (Static Random Access Memory) cells fabricated with blanket SOI (Silicon On Insulator) provide better soft error immunity (immunity from errors caused by cosmic radiation such as alpha and gamma rays) and faster performance than SRAM cells fabricated in bulk silicon. SRAM cells fabricated with blanket SOI also advantageously allow tighter/closer n+/p+ spacing, as shown in FIGS. 1-3 herein, for more compact memory cell layouts. However, the SRAM cell size is not reduced when the SRAM cell design in bulk silicon is migrated or transferred to a SRAM cell design in SOI, as shown in FIGS. 1-3. Moreover, the effect of the floating (not coupled to a reference voltage or ground) bodies of the passgate devices (the silicon above the insulator is not coupled to ground in SOI as in bulk silicon) of the SRAM memory cells in SOI make the SRAM cells more susceptible to access disturbs than SRAM cells fabricated in bulk silicon. The floating bodies of the passgate devices in SOI degrade the cell stability because the passgate devices are more conductive in SOI than in bulk silicon. The unselected SRAM memory cells along a selected wordline in SOI can erroneously change states more easily because the down node (connected to ground) can be pulled up more easily through the passgate devices. The floating bodies of the pull-up and pull-down devices also tend to make the off devices turn on more easily in SOI than in bulk silicon.
Thus SRAM cells fabricated in bulk silicon may have a beta ratio <1.5, while SRAM cells fabricated in blanket SOI must have a beta ratio >2.1. The beta ratio here refers to the ratio of electrical W/L (Width/Length ratio) of the pull-down NFETs compared to the electrical W/L of the passgate NFETs. When the design of a SRAM cell fabricated in bulk silicon is migrated or transferred to the design of a SRAM cell fabricated in SOI, the flexibility of an active well is also lost. An active well is necessary for control of the SRAM cell circuit speed and off currents. An active well can be moved/biased up and down in voltage to control the circuit speed and off currents, whereas in SOI the well floats and cannot be moved/biased up and down in voltage.
FIG. 1 illustrates the layout of a SRAM cell fabricated in bulk silicon, and shows the PC (polysilicon conductor) and RX (active silicon conductor regions which are isolated by trench isolation regions) areas and regions of the chip and the M1 metal level (the first and lowest metal level). FIG. 2 illustrates the layout of a SRAM cell fabricated in blanket SOI, and shows the PC and RX areas and regions of the chip and the M1 metal level. FIG. 3 illustrates a simplified version of FIG. 2, and shows only the PC and RX areas and regions of the chip, and the M1 metal level is not shown.
All dimensions shown in FIGS. 1-5 are in microns, and the bottom of FIGS. 1-4 also show the dimensions in microns of the overall layout dimensions of each SRAM cell.
FIG. 1 illustrates a top plan view of a circuit layout of a prior art 90 nm node technology SRAM cell fabricated in bulk silicon. FIG. 1 illustrates only the PC (polysilicon conductor) areas, the RX (active silicon conductor regions which are isolated by trench isolation regions) regions, and the M1 (first metal) level of the chip, and the M2 and M3 (second and third metal) levels are not shown.
The prior art 90 nm node technology SRAM cell is fabricated in a base PC (Polysilicon Conductor) level, the overlying bottom M1 metal level, the next higher metal level M2, and the next higher metal layer M3. The prior art 90 nm node technology SRAM cell is fabricated with a PC level wordline WL and an M2 metal level ground, VDD power supply and bitlines BLs. For large SRAM cell arrays, the PC level is not an efficient enough conductor for the global wordlines, and the M3 metal level must be used for the global wordlines.
FIG. 5 illustrates a circuit schematic of a SRAM cell fabricated in either bulk silicon, blanket SOI or SSOI. The circuit of the SRAM cell is well known and includes cross coupled pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply VDD, and the N1, N2 devices being connected to ground GND. The left npn passgate device NL is coupled between the left bitline BL and the junction of devices P1 and N1, with its gate coupled to the wordline WL. The right npn passgate device NR is coupled between the right bitline BR and the junction of devices P2 and N2, with its gate coupled to the wordline WL.
Referring to FIG. 1 which illustrates a SRAM cell fabricated in bulk silicon and to FIG. 2 which illustrates a SRAM cell fabricated in SOI, the PC level wordline WL extends generally horizontally across the lower portion of the chip and crosses left and right legs of a bottom M shaped RX (active silicon conductor) region, with the crossing on the left defining the passgate device NL, with the WL defining the gate G and the RX region defining the source S and drain D regions of the passgate NL, and with the crossing on the right defining the passgate device NR, with the WL defining the gate G and the RX region defining the source S and drain D regions of the passgate device NR.
Left and right PC (Polysilicon Conductor) regions extend vertically on opposite left and right portions of the chip as shown in FIGS. 1 and 2.
The top horizontal portion of the bottom M shaped RX region crosses the left PC region and defines the pulldown device N1, with the left PC region defining the gate G and the RX region defining the drain D and source S regions of the pulldown device N1. The top horizontal portion of the M shaped RX region crosses the right PC region and defines the pulldown device N2, with the right PC region defining the gate G and the RX region defining the source S and drain D regions of the pulldown device N2, with a common source region S between the pulldown devices N1 and N2.
A horizontal base of a top W shaped RX (active silicon conductor) region crosses the upper portions of the left and right PC regions.
The bottom horizontal portion of the top W shaped RX region crosses the left PC region and defines the pullup device P1, with the left PC region defining the gate G and the RX region defining the drain D and source S regions of the pullup device P1. The bottom horizontal portion of the W shaped RX region crosses the right PC region and defines the pullup device P2, with the right PC region defining the gate G and the RPX region defining the source S and drain D regions of the pullup device P2, with a common source region S between the pullup devices P1 and P2.
In the design and layout of FIG. 2, the beta ratio has been increased, relative to the design and layout of FIG. 1, from 1.67 to 2.32, with the pull down device width labeled PDW, being increased from 0.266 to 0.364 microns. To maintain the same cell size, the n+/p+ spacing, labeled n+p+S, is reduced to 0.406 from 0.504 microns, while also reducing the M1 metal level dimensions somewhat. The smaller n+/p+ spacing is possible because SOI helps to isolate the deep well leakage.